DESCRIPTION

s 365ps propagation delay

s 2.0GHz toggle frequency

s Internal 75K

s Available in 8-pin SOIC package

The SY10/100EL52 are differential data, differential

clock D flip-flops. These devices are functionally

equivalent to the E452 devices, with higher performance

capabilities. With propagation delays and output transition

times significantly faster than the E452, the EL52 is ideally

suited for those applications which require the ultimate

in AC performance.

Data enters the master portion of the flip-flop when

the clock is LOW and is transferred to the slave, and

thus the outputs, upon a positive transition of the clock.

The differential clock inputs also allow the EL52 to be

used as a negative edge triggered device.

The EL52 employs input clamping circuitry so that,

outputs of the device will remain stable.

FEATURES

DIFFERENTIAL DATA AND

CLOCK D FLIP-FLOP

PIN CONFIGURATION/BLOCK DIAGRAM

D

CLK

Q

LZ

L

HZ

H

NOTE:

1. Z = LOW-to-HIGH transition.

SOIC

TOP VIEW

Pin

Function

D

Data Input

CLK

Clock Input

Q

Data Output

1

2

3

45

6

7

8

Q

Q

CLK

Flip-Flop

D

CLK

D

Rev.: F

Amendment: /0

Issue Date:

August, 1998

SY10EL52

SY100EL52

PIN NAMES

1