TRUTH TABLE

PIN NAMES

DESCRIPTION

Pin

Function

Differential Data Inputs

Mux Select Inputs

Reference Outputs

Q

Data Outputs

SEL1

SEL0

DATA OUT

LL

LH

HL

HH

FEATURES

PIN CONFIGURATION/BLOCK DIAGRAM

s Useful as either 4:1 or 2:1 multiplexer

s 75K

s Available in 150 mil 16-pin SOIC package

The SY10/100EL57 are fully differential 4:1 multiplexers.

By leaving the SEL1 line open (pulled LOW via the input

pulldown resistors) the device can also be used as a

differential 2:1 multiplexer with SEL0 input selecting between

D0 and D1. The fully differential architecture of the EL57

makes it ideal for use in low skew applications such as

clock distribution.

The SEL1 is the most significant select line. The binary

number applied to the select inputs will select the same

numbered data input (i.e., 00 selects D0).

should be connected to the data bar inputs and bypassed

via a 0.01

can source/sink up to 0.5mA of current without upsetting

the voltage level.

4:1 DIFFERENTIAL

MULTIPLEXER

SY10EL57

SY100EL57

FINAL

SOIC

TOP VIEW

4:1

D0

1

234

5

6

7

8

D0

D1

D1

D2

D2

D3

D3

16

15

14

13

12

11

10

9

SEL0

SEL1

Q

Q

1

Rev.: F

Amendment: /0

Issue Date:

February 2003