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SY10EL32VZCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10EL32VZCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page DESCRIPTION s 3.3V and 5V power supply options s 510ps propagation delay s 3.0GHz toggle frequency s High bandwidth output transistions s Internal 75K Ω input pull-down resistors s Available in 8-pin SOIC package The SY10/100EL32V are integrated ÷2 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple EL32Vs in a system. FEATURES PIN CONFIGURATION/BLOCK DIAGRAM PIN NAMES 5V/3.3V ÷ 2 DIVIDER SOIC TOP VIEW Pin Function CLK Clock Inputs Reset Asynchronous Reset VBB Reference Voltage Output Q Data Outputs 1 2 3 4 5 6 7 8 Reset VCC Q VEE CLK VBB Q R CLK ÷ 2 Rev.: C Amendment: /0 Issue Date: August, 1998 ClockWorks™ SY10EL32V SY100EL32V 1 |
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