TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I

SDA

SCL

P

S

Sr

S

T0114-01

TAS5086

Devices

F/S-Mode I2C-Bus Devices).

A

STANDARD MODE

FAST MODE

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

SCL clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

4

0.6

µs

generated.

LOW period of the SCL clock

4.7

1.3

µs

HIGH period of the SCL clock

4

0.6

µs

Setup time for repeated START

4.7

0.6

µs

Data setup time

250

100

µs

0

3.45

0

0.9

µs

Rise time of both SDA and SCL

1000

(3)

ns

Fall time of both SDA and SCL

300

(3)

300

ns

Setup time for STOP condition

4

0.6

µs

Bus free time between a STOP and

4.7

1.3

µs

START condition

Capacitive loads for each bus line

400

400

pF

Noise margin at the LOW level for each

V

connected device (including hysteresis)

Noise margin at the HIGH level for each

V

connected device (including hysteresis)

(1)

of SCL. TI recommends that a 3.3-k

Ω pullup resistor be used to avoid potential timing issues.

(2)

This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

(3)

(4)

Rise time varies with pullup resistor.

Figure 3. Start and Stop Conditions Timing Waveforms

6

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