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SY100E431JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100E431JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page DESCRIPTION FEATURES s Differential D, clock and Q s Extended 100E VEE range of –4.2V to –5.5V s VBB output for single-ended use s 1100MHz min. toggle frequency s Edge-triggered asynchronous set and reset s Fully compatible with Motorola MC10E/100E431 s Available in 28-pin PLCC package The SY10/100E431 are 3-bit flip-flops with differential clock, data input and data output. The asynchronous Set and Reset controls are edge- triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduces the metastability susceptibility window. 3-BIT DIFFERENTIAL FLIP-FLOP SY10E431 SY100E431 BLOCK DIAGRAM D0 D0 Q0 Q0 VBB CLK0 CLK0 S0 R0 DQ Q S R D1 D1 Q1 Q1 CLK1 CLK1 S1 R1 DQ Q S R D2 D2 Q2 Q2 CLK2 CLK2 S2 R2 DQ Q S R Pin Function D[0:2], D[0:2] Differential Data Inputs CLK[0:2], CLK[0:2] Differential Clock Inputs S[0:2] Edge Triggered Set Inputs R[0:2] Edge Triggered Reset Inputs VBB VBB Reference Output Q[0:2], Q[0:2] Differential Data Outputs VCCO VCC to Output PIN NAMES PIN CONFIGURATION Rev.: C Amendment: /1 Issue Date: February, 1998 18 17 16 15 14 13 12 56 7 8 9 10 11 26 27 28 1 2 3 4 TOP VIEW PLCC J28-1 25 24 23 22 21 20 19 CLK1 R1 VEE S1 D1 CLK1 D1 Q2 VCC Q1 Q0 Q2 Q1 Q0 Dn CLKn Rn Sn Qn LZ L L L HZ L L H XL Z L L XL L Z H TRUTH TABLE(1) NOTE: 1. Z = LOW-to-HIGH transition. 1 |
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