DESCRIPTION

FEATURES

The SY10/100E431 are 3-bit flip-flops with differential

clock, data input and data output.

The asynchronous Set and Reset controls are edge-

triggered rather than level controlled. This allows the user

to rapidly set or reset the flip-flop and then continue

clocking at the next clock edge without the necessity of

de-asserting the set/reset signal (as would be the case

with a level controlled set/reset).

The E431 is also designed with larger internal swings,

an approach intended to minimize the time spent crossing

the threshold region and thus reduces the metastability

susceptibility window.

3-BIT DIFFERENTIAL

FLIP-FLOP

SY10E431

SY100E431

BLOCK DIAGRAM

DQ

Q

S

R

DQ

Q

S

R

DQ

Q

S

R

Pin

Function

D[0:2], D[0:2]

Differential Data Inputs

CLK[0:2], CLK[0:2]

Differential Clock Inputs

S[0:2]

Edge Triggered Set Inputs

R[0:2]

Edge Triggered Reset Inputs

Q[0:2], Q[0:2]

Differential Data Outputs

PIN NAMES

PIN CONFIGURATION

Rev.: C

Amendment: /1

Issue Date:

February, 1998

18

17

16

15

14

13

12

56

7

8

9

10 11

26

27

28

1

2

3

4

TOP VIEW

PLCC

J28-1

25 24 23 22 21 20 19

LZ

L

L

L

HZ

L

L

H

XL

Z

L

L

XL

L

Z

H

NOTE:

1. Z = LOW-to-HIGH transition.

1