7

FN8158.3

February 13, 2008

Write in Process (WIP bit)

The contents of the Data Registers are saved to nonvolatile

memory when the CS pin goes from LOW to HIGH after a

complete write sequence is received by the device. The

progress of this internal write operation can be monitored by

a Write In Process bit (WIP). The WIP bit is read with a Read

Status command (See Figure 4).

Power-up and Down Requirements

At all times, the V+ voltage must be greater than or equal to

greater than or equal to the voltage at V-. During power-up

values within 1msec of each other.

ID3

ID2

ID1

ID0

0

0

A0

I2

I1

I0

RB

RA

SCK

SI

CS

0101

R/W

DEVICE ID

INTERNAL

INSTRUCTION

OPCODE

ADDRESS

REGISTER

0

0

0

0

ADDRESS

0

0

0

FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE

ID3 ID2 ID1 ID0 0

A0 R/W I2

00

SCK

SI

0

0

X

X0

0

XX

X

W

C

R

9

W

C

R

8

W

C

R

7

W

C

R

6

W

C

R

5

W

C

R

4

W

C

R

3

W

C

R

2

W

C

R

1

W

C

R

0

CS

I1

I0 0 RB RA

0

101

0

XX

X

DEVICE ID

INTERNAL

ADDRESS

INSTRUCTION

OPCODE

REGISTER

ADDRESS

WIPER

POSITION

0

FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)

ID3 ID2 ID1 ID0 0

A0 R/W I2

00

SCK

SI

1

0

X

X0

0

XX

X

WIP

CS

I1

I0

0 RB RA

01

0

1

0

XX

X

DEVICE ID

INTERNAL

ADDRESS

INSTRUCTION

OPCODE

REGISTER

ADDRESS

STATUS

BIT

X X

0

00

0 0

0 0

0

0

FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)

X9110