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SY10E107 Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10E107 Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page s 600ps max. propagation delay s Extended 100E VEE range of –4.2V to –5.5V s True and complementary outputs s OR/NOR function outputs s Fully compatible with Industry standard 10KH, 100K I/O levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E107 s Available in 28-pin PLCC package The SY10/100E107 offer five 2-input XOR/XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and complementary outputs are provided. QUINT 2-INPUT XOR/XNOR GATE FEATURES DESCRIPTION SY10E107 SY100E107 Rev.: C Amendment: /1 Issue Date: February, 1998 PIN CONFIGURATION Pin Function Dna, Dnb Data Inputs Q0-Q4 XOR Outputs Q0-Q4 XNOR Outputs F OR Output F NOR Output VCCO VCC to Output PIN NAMES VEE D3b D2a D1b D1a 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 56789 10 11 D0a D2b Q4 PLCC TOP VIEW J28-1 Q4 VCC Q3 Q3 Q2 Q2 BLOCK DIAGRAM D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 F F Q4 Q4 1 |
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