Pin

Function

Bus Enable Inputs

Data Inputs

Bus Driver Clock Input

Receive Register Clock

MR

Master Reset

Bus Receive Outputs

Bus Outputs

DESCRIPTION

FEATURES

s 25

s 50

s Transmit and receive registers with separate clocks

s Individual bus enable pins

s Internal 75K

s Voltage and temperature compensation for improved

noise immunity

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Available in 28-pin PLCC package

The SY100S891 is a 5-bit registered transceiver

containing five bus transceivers with both transmit and

specified for driving a 25 ohm bus and the receive outputs

bus outputs have a normal high level output voltage and

a normal low level output voltage when the bus enable

switched to a cut-off level when a bus-enable is low.

This cut-off level is sufficiently low that a relatively high

impedance is presented to the bus in order to minimize

reflections. There is one bus-enable for each bus driver;

to all five receive registers. Data at the D inputs is clocked

data on the bus is clocked into the Receiver register by

clears all registers.

5-BIT REGISTERED

TRANSCEIVER

PIN CONFIGURATION

PIN NAMES

SY100S891

Rev.: E

Amendment: /0

Issue Date: August, 1998

TOP VIEW

PLCC

J28-1

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25

24 23 22

21 20

19

56

789

10 11

MR

1