The SY100S834/L is low skew (

÷1, ÷2, ÷4) or (÷2,

÷4, ÷8) clock generation chip designed explicitly for low

skew clock generation applications. The internal dividers

are synchronous to each other, therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL or,

if positive power supplies are used, PECL input signal.

can be AC-coupled into the device. If a single-ended

to the CLK input and bypassed to ground via a 0.01

µF

switching reference for the input of the SY100S834/L

under single-ended input conditions. As a result, this pin

can only source/sink up to 0.5mA of current.

is LOW, SY100S834/L functions as a divide by 2, by 4

is HIGH, it functions as a divide by 1, by 2 and by 4

clock generation chip. This latter feature will increase

the clock frequency by two folds.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S834/Ls in a system.

DESCRIPTION

s 3.3V and 5V power supply options

s 50ps output-to-output skew

s Synchronous enable/disable

s Master Reset for synchronization

s Internal 75K

s Available in 16-pin SOIC package

FEATURES

Rev.: F

Amendment: /0

Issue Date: September, 1999

(

CLOCK GENERATION CHIP

ClockWorks™

SY100S834

SY100S834L

Pin

Function

CLK

Differential Clock Inputs

Function Select

EN

Synchronous Enable

MR

Master Reset

Reference Output

Differential

÷1 or ÷2 Outputs

Differential

÷2 or ÷4 Outputs

Differential

÷4 or ÷8 Outputs

PIN NAMES

CLK

EN

MR

Function

Z

L

L

Divide

ZZ

H

L

X

X

H

NOTES:

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

TRUTH TABLE

L

Divide by 2

Divide by 4

Divide by 8

H

Divide by 1

Divide by 2

Divide by 4

PIN CONFIGURATION/BLOCK DIAGRAM

SOIC

TOP VIEW

EN

CLK

CLK

MR

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

Q

R

Q

R

÷1 or ÷2

Q

Q

R

R

D

÷2 or ÷4

÷4 or ÷8

1