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IPC302N20N3 Datasheet(PDF) 2 Page - Infineon Technologies AG |
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IPC302N20N3 Datasheet(HTML) 2 Page - Infineon Technologies AG |
2 / 4 page 2 OptiMOS™3PowerMOSTransistorChip IPC302N20N3 Rev.2.6,2015-04-08 Final Data Sheet PowerMOSTransistorChip Drain Gate Source 1Description •N-channelenhancementmode •Foradditionalcharacteristicandmaxratingsrefertothedatasheetof IPP110N20N3G •AQL0.65forvisualinspectionaccordingtofailurecatalogue •ElectrostaticDischargeSensitiveDeviceaccordingtoMIL-STD883C •Diebond:solderedorglued •Backsidemetallization:NiVsystem •Frontsidemetallization:AlCusystem •Passivation:nitride(onlyonedgestructure) Table1KeyPerformanceParameters Parameter Value Unit V(BR)DSS 200 V RDS(on) 12 1) m Ω Die size 6.7 x 4.5 mm 2 Thickness 250 µm Type/OrderingCode Package Marking RelatedLinks IPC302N20N3 Chip not defined - 2ElectricalCharacteristicsonWaferLevel atTj=25°C,unlessotherwisespecified Table2 Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Drain-source breakdown voltage V(BR)DSS 200 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 2 3 4 V VDS=VGS,ID=260µA Zero gate voltage drain current IDSS - 0.1 1 µA VGS=0V,VDS=160V Gate-source leakage current IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on- resistance RDS(on) - 9.2 2) 100 3) m Ω VGS=10V,ID=2.0A Reverse diode forward on-voltage VSD - 1.0 1.2 V VGS=0V,IF=1A Avalanche energy, single pulse EAS - 47 4) - mJ ID =30 A, RGS =25 Ω 1) packaged in a P-TO220-3 (see ref. product) 2)typicalbaredieRDS(on);VGS=10V 3) limited by wafer test-equipment 4) Wafer tested. For general avalanche capability refer to the datasheet of IPP110N20N3 G |
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Similar Description - IPC302N20N3 |
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