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SY100S318JCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S318JCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 5 page BLOCK DIAGRAM D1a D2a D3a D4a D5a D1b D2b D3b D4b O O D1c D2c D3c D4c D1d D2d D3d D4d D1e D2e SY100S318 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE FEATURES PIN CONFIGURATIONS DESCRIPTION Pin Function Dna – Dne Data Inputs (n = 1...5) O – O Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES O O VCCA VCC D2e VCC D2b VEE D4b D3b D1c VEES 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 Top View PLCC J28-1 D1e D2c 26 18 25 5 D1b D5a D4a D3a D1a D2a D3c D1d D3d D4c D4d D2d 18 17 16 15 14 13 1 2 3 4 5 6 7 24 8 23 9 22 10 21 11 20 12 19 Top View Flatpack F24-1 Rev.: G Amendment: /0 Issue Date: July, 1999 s Max. propagation delay of 800ps s IEE min. of –55mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s 70% faster than Fairchild s 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gate with both true and complementary outputs, designed for use in high-performance ECL systems. The inputs on this device have 75K Ω pull-down resistors. 1 |
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