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ISL98001IQZ-140 Datasheet(PDF) 18 Page - Intersil Corporation |
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ISL98001IQZ-140 Datasheet(HTML) 18 Page - Intersil Corporation |
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18 / 31 page  18 FN6148.5 September 21, 2010 Technical Highlights The ISL98001 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically this has been implemented as a traditional analog PLL. At SXGA and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). As display resolutions and refresh rates have increased, however, the pixel period has shrunk. An XGA pixel at a 60Hz refresh rate has 15.4ns to change and settle to its new value. But at UXGA 75Hz, the pixel period is 4.9ns. Most consumer graphics cards (even the ones with “350MHz” DACs) spend most of that time slewing to the new pixel value. The pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. In many cases it rings and never settles at all. So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The ISL98001's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64-phase steps per pixel (vs the industry standard 32), for fine, accurate positioning of the sampling point. The crystal- locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. An intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10MHz or higher) to UXGA 60Hz (170MHz, with the ISL98001-170). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. 0x25 Sync Separator Control (0x00) 0 Three-state Sync Outputs 0: VSYNCOUT, HSYNCOUT, VSOUT, HSOUT are active (default). 1: VSYNCOUT, HSYNCOUT, VSOUT, HSOUT are in three-state. 1 COAST Polarity 0: Coast active high (default) 1: Coast active low Set to 0 for internal VSYNC extracted from CSYNC. Set to 0 or 1 as appropriate to match external VSYNC or external COAST. 2HSOUT Lock Edge 0: HSOUT's trailing edge is locked to selected HSYNCIN's lock edge. Leading edge moves backward in time as HSOUT width is increased (X980xx default). 1: HSOUT's leading edge is locked to selected HSYNCIN's lock edge. Trailing edge moves forward in time as HSOUT width is increased. 3 Reserved Set to 0 4 VSYNCOUT Mode 0: VSYNCOUT is aligned to HSYNCOUT edge, providing “perfect” VSYNC signal (default). 1: VSYNCOUT is “raw” integrator output. 5 Reserved Set to 0 6 Reserved Set to 0 7VSOUT Mode 0: VSOUT is output on VSOUT pin (default). 1: COAST (including pre- and post-coast COAST) is output on VSOUT pin. 0x2B Crystal Multiplier (0x14) 7:0 Crystal Multiplier When using the ISL98001-275, the value in this register must need to be changed to achieve the maximum conversion rate (see “Initialization” on page 26. This register may also be adjusted to lower power consumption at slower pixel rates (see the “Reducing Power Dissipation” on page 26 for more information). Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION ISL98001 |
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