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LMC7225IM5 Datasheet(PDF) 10 Page - Texas Instruments |
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LMC7225IM5 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page LMC7215, LMC7225 SNOS882E – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com Figure 17. RS = 10Ω Figure 18. LATCH-UP In the past, most CMOS IC's were susceptible to a damaging phenomena known as latch-up. This occurred when an ESD current spike or other large signal was applied to any of the pins of an IC. The LMC7215 and LMC7225 both are designed to make them highly resistant to this type of damage. They have passed qualification tests with input currents on any lead up to 300 mA at temperatures up to 125°C. SPICE MODELS For a SPICE model of the LMC7215, LMC7225 and many other op amps and comparators, visit www.ti.com. 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7215 LMC7225 |
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