Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

TDA21231 Datasheet(PDF) 10 Page - Infineon Technologies AG

Part No. TDA21231
Description  DrMOS Product Family
Download  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TDA21231 Datasheet(HTML) 10 Page - Infineon Technologies AG

Back Button TDA21231_15 Datasheet HTML 6Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 7Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 8Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 9Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 10Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 11Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 12Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 13Page - Infineon Technologies AG TDA21231_15 Datasheet HTML 14Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 19 page
background image
TDA21231
Data Sheet
9
Referring to the block diagram page 4, VCC is internally connected to the UVLO circuit. It will force shut-down
for insufficient VCC voltage. PVCC supplies the floating high-side drive
– consisting of an active boot circuit -
and the low side drive circuit. During undervoltage both GH and GL are driven low actively; further passive pull-
down (10 k
) is placed across gate-source of both FETs.
An additional UVLO circuitry, sensing the BOOT voltage level, is implemented to enable a recharge of the boot
capacitor when its voltage is too low for a complete turn-on of the HS-MOSFET.
5.2
Inputs to the Internal Control Circuits
The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V.
The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for
at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET
gate outputs low. Once left open, the pin is held internally at a level of VPWM_O = 1.6 V level.
Table 12
PWM Pin Functionality
PWM logic level
Driver output
Low
GL= High, GH = Low
High
GL = Low, GH = High
Open (left floating, or High impedance)
GL = Low, GH = Low
The PWM threshold voltages VPMW_O, VPWM_H, VPWM_L do not vary over the wide range of VCIN supply
voltages (4.5 V to 8 V).
The EN is an active high signal. When EN is being pulled low, the power stage will be disabled.
Figure 4
Enable (EN) signal logic levels
VCC
“H”
“L”
VEN_L
VEN_H
EN Logic
Level
Shutdown
Enable


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn