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PSMN4R5-40BS Datasheet(PDF) 3 Page - NXP Semiconductors |
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PSMN4R5-40BS Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 15 page PSMN4R5-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 22 March 2012 3 of 15 NXP Semiconductors PSMN4R5-40BS N-channel 40 V 4.5 m Ω standard level MOSFET in D2PAK 5. Limiting values [1] Continuous current is limited by package Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =20 kΩ -40 V VGS gate-source voltage -20 20 V ID drain current VGS =10 V; Tmb = 100 °C; see Figure 1 [1] -96 A VGS =10 V; Tmb =25°C; see Figure 1 [1] - 100 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; see Figure 3 - 545 A Ptot total power dissipation Tmb =25°C; see Figure 2 - 148 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb =25°C [1] - 100 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 545 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS =10 V; Tj(init) =25°C; ID =100 A; Vsup ≤ 40 V; unclamped; RGS =50 Ω - 152 mJ Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aad008 0 50 100 150 0 50 100 150 200 Tmb ( °C) ID (A) (1) Tmb (°C) 0 200 150 50 100 03aa16 40 80 120 Pder (%) 0 |
Similar Part No. - PSMN4R5-40BS_15 |
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