MX98728EC datasheet(32/71 Pages) MCNIX

Part #	MX98728EC

Description	GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

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Manufacturer	MCNIX [Macronix International]

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32

P/N:PM0723

REV. 1.0, JUL. 13, 2000

MX98728EC

For a successful transmission, an interrupt is caused

by the interrupt register bit TI ( bit 2 of register 09h ) of

the interrupt register IR, provided that the correspond-

ing enable bit TIM ( bit 2 of register 08h ) of the interrupt

enable register IMR is set. In case that an error occurred

during the transmission, the interrupt register bit TEI will

be set instead of TI. The register 09h bit 4 ( TEIM ) is

the interrupt enable bit for TEI. Set TEIM will enable the

TEI interrupt. The transmission error can be read from

register 04h ( the LTPS register ) which records the trans-

mit status of the last packet transmitted. If bit 7 ( TERR

) of register 04h is set, then TEI will be set as well. TERR

is a logical OR of the underrun error( UF bit ), the out-of-

window collision error ( OWC bit ), the carrier lost error (

CRSLOST bit ) and the excessive collision error (

CC[3:0]=1111 and TEI = 1).

Collision recovery

During transmission, if a collision is detected before the

first 64 bytes of the the packet has been transmitted,

the FIFO will restore the necessary FIFO pointers to

retransmit the same packet without fetching the trans-

mitted data from the packet memory. An out-of-window

collision is a collision occured after 64 bytes of data

transmitted. If the out-of-window collision occurred, the

packet will be aborted with an interrupt asserted. The

OWC bit of the transmit descriptor is set and the device

driver needs to resolve such a situation and reissue a

transmit command so that GMAC can fetch the entire

packet from the packet memory again for retransmis-

sion.

The collision count will be recorded for the current packet

in register 04h.CC[3:0] bits. If all 15 retransmissions

result in collisions, the transmission is aborted and the

collision count CC[3:0]=1111 and an interrupt will be as-

serted and the TEI interrupt bit is set to indicate such an

excessive collision error. If the TI interrupt bit is set,

then the packet is successfully transmitted with the col-

lision count=CC[3:0].

After a single packet transmission

When a packet(s) transmission is completed, register

00h.ST1 and ST0 are both cleared to 0 automatically by

GMAC. Whenever the first packet is sent out, an inter-

rupt is asserted for the host attention. The device driver

can process this packet's status. In the TX local DMA

mode, the first thing to check is making sure the OWN

bit in the status field bit 7 is 0, which indicates that GMAC

has completed the transmission of this packet and the

status is valid. Or in the direct FIFO mode, check ST1

and ST0 for both 0, which indicates completion of the

previous transmission. At this point, the device driver

can proceed with the transmit status ( on the register or

in the descriptor ) and other book keeping tasks. If host

system does not support SRDY pin, the following flow

chart provides a way to fetch transmit status of any

transmitted packet in the packet memory in TX DMA

mode. This is useful when multiple packets are trans-

mitted in a single command and multiple transmit status

needed to be checked.

START

Yes

read?

End

Yes

Write starting page address to IORDP

(1E/1F)

Read

RRDYB

(3A.1)==0?

Write "1" to STIORD/ RRDYB

(3A.1)

Read back Data from IORD (4C-4F)

No

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