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MX29F100TTA-90 Datasheet(PDF) 13 Page - Macronix International

Part No. MX29F100TTA-90
Description  1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com

MX29F100TTA-90 Datasheet(HTML) 13 Page - Macronix International

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REV. 1.2, NOV. 12, 2001
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
This allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this case
the device locks out and never completes the Automatic
Algorithm operation. Hence, the system never reads a
valid data on Q7 bit and Q6 never stops toggling. Once
the Device has exceeded timing limits, the Q5 bit will
indicate a "1". Please note that this is not a device failure
condition since the device was incorrectly used.
Sector Erase Timer
After the completion of the initial sector erase command
sequenc the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent commands
to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit. If
Q3 is low ("0"), the device will accept additional sector
erase commands. To insure the command has been
accepted, the system software should check the status of
Q3 prior to and following each subsequent sector erase
command. If Q3 were high on the second status check,
the command may not have been accepted.
Reading Toggle Bits Q6
Whenever the system initally begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program ot erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and Q5
through successive read cycles, determining the status
as described in the previous paragraph. Alternatively, it
may choose to perform other system tasks. In this case,
the system must start at the beginning of the algorithm
when it returns to determine the status of the operation.

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