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MX29F100TTA-90 Datasheet(PDF) 12 Page - Macronix International

Part No. MX29F100TTA-90
Description  1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com
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MX29F100TTA-90 Datasheet(HTML) 12 Page - Macronix International

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12
P/N:PM0548
MX29F100T/B
REV. 1.2, NOV. 12, 2001
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions.Another Erase Suspend command can be
written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, a three-cycle
command sequence is required. There are two "un-
lock" write cycles. These are followed by writing the
Automatic Program command A0H.
Once the Automatic Program command is initiated,
the next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE pulse. The rising edge of WE
also begins the programming operation. The system
is not required to provide further controls or timings.
The device will automatically provide an adequate
internally generated program pulse and verify margin.
If the program opetation was unsuccessful, the data
on Q5 is "1"(see Table 4), indicating the program
operation exceed internal timing limit. The automatic
programming operation is completed when the data
read on Q6 stops toggling for two consecutive read
cycles and the data on Q7 and Q6 are equivalent to
data written to these two bits, at which time the device
returns to the Read mode(no program verify command
is required).
WRITE OPERATION STATUS
DATA POLLING-Q7
The MX29F100T/B also features Data Polling as a method
to indicate to the host system that the Automatic Program
or Erase algorithms are either in progress or completed.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an attempt
to read the device will produce the true data last written
RY/BY:Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid after
the rising edge of the final WE pulse in the command
sequence. Since RY/BY is an open-drain output, several
RY/BY pins can be tied together in parallel with a pull-up
resistor to Vcc.
If the outputs is low (Busy), the device is actively erasing
or programming.
(This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
TOGGLE BIT-Q6
The MX29F100T/B features a "Toggle Bit" as a method to
indicate to the host system that the Auto Program/Erase
algorithms are either in progress or completed.
While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in Q6 toggling between one and zero.
Once the Automatic Program or Erase algorithm is
completed, Q6 will stop toggling and valid data will be
read. The toggle bit is valid after the rising edge of the
sixth WE pulse of the six write pulse sequences for chip/
sector erase.
The Toggle Bit feature is active during Automatic Program/
Erase algorithms or sector erase time-out.(see section
Q3 Sector Erase Timer)
to Q7. The Data Polling feature is valid after the rising edge
of the fourth WE pulse of the four write pulse sequences
for automatic program.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will read
"1". The Data Polling feature is valid after the rising edge
of the sixth WE pulse of six write pulse sequences for
automatic chip/sector erase.
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)


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