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MX29F100TTA-90 Datasheet(PDF) 9 Page - Macronix International

Part No. MX29F100TTA-90
Description  1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com

MX29F100TTA-90 Datasheet(HTML) 9 Page - Macronix International

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REV. 1.2, NOV. 12, 2001
The read or reset operation is initiated by writing the
read/reset command sequence
into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
If program-fail or erase-fail happen, the write of F0H
will reset the device to abort the operation. A valid
command must then be written to place the device in
the desired state.
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais-
ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not generally desired
system design practice.
The MX29F100T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle
with A1=VIL, A0=VIL retrieves the manufacturer code
of C2H/00C2H. A read cycle with A1=VIL, A0=VIH
returns the device code of D9H/22D9H for
MX29F100T, DFH/22DFH for MX29F100B.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing
the "set-up" command 80H. Two more "unlock" write
cycles are then followed by the chip erase command
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify
begin. The erase and verify operations are completed
when the data on Q7 is "1" at which time the device
returns to the Read mode. The system is not required
to provide any control or timing during these
When using the Automatic Chip Erase algorithm, note
the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verified command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and
terminates when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode.

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