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MX28F1000P Datasheet(PDF) 1 Page - Macronix International

Part No. MX28F1000P
Description  1M-BIT [128K x 8] CMOS FLASH MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com
Logo MCNIX - Macronix International

MX28F1000P Datasheet(HTML) 1 Page - Macronix International

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• 131,072 bytes by 8-bit organization
• Fast access time: 70ns(Vcc:5V±5%; CL:35pF)
90/120ns(Vcc:5V±10%; CL:100pF)
• Low power consumption
– 50mA maximum active current
– 100uA maximum standby current
• Programming and erasing voltage 12V ± 5%
• Command register architecture
– Byte Programming (15us typical)
– Auto chip erase 5 seconds typical
(including preprogramming time)
– Block Erase
• Optimized high density blocked architecture
– Four 4-KB blocks
P/N: PM0340
REV. 1.6,JAN. 19, 1999
The MX28F1000P is a 1-mega bit Flash memory or-
ganized as 128K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F1000P is packaged in 32-pin PDIP, PLCC
and TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
The standard MX28F1000P offers access times as
fast as 70 ns, allowing operation of high-speed
microprocessors without wait states.
To eliminate
bus contention, the MX28F1000P has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
programming. The MX28F1000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout.
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms.
In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
uses a 12.0V ± 5% VPP supply to
perform the Auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
– Seven 16-KB blocks
• Auto Erase (chip & block) and Auto Program
– DATA polling
– Toggle bit
• 10,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Advanced CMOS Flash memory technology
• Compatible with JEDEC-standard byte-wide 32-pin
EPROM pinouts
• Package type:
– 32-pin plastic DIP
– 32-pin PLCC
– 32-pin TSOP (Type 1)

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