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ISL51002CQZ-110 Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL51002CQZ-110 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 33 page 9 FN6164.3 February 29, 2012 Pin Descriptions SYMBOL DESCRIPTION RIN0, 1, 2 Analog inputs. Red channels. AC couple through 0.1µF. Do not connect if not used. GIN0, 1, 2 Analog inputs. Green channels. AC couple through 0.1µF. Do not connect if not used. BIN0, 1, 2 Analog inputs. Blue channels. AC couple through 0.1µF. Do not connect if not used. VREFRED, VREFGREEN, VREFBLUE Analog inputs. Reference voltage for ADCs. Tie to 1.8V reference voltage (VA1.8 is acceptable if low noise). Decouple with 0.1µF capacitor to GNDA. SOGIN0, 1, 2 Analog inputs. Sync on Green. Connect to corresponding Green channel video source through a 0.01µF capacitor in series with a 500 Ω resistor. HSYNCIN0, 1, 2 Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's HSYNC source. For 5V signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pFcapacitor in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GNDD if not used. VSYNCIN0, 1, 2 Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's VSYNC source. For 5V signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pF capacitor in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GNDD if not used. COASTIN Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transitions on the active channel’s HSYNC/SOG. CLAMPIN Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the clamp DAC. CLOCKINVIN Digital 3.3V input. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to DGND if unused. FBCIN Digital 3.3V input.Connect to the Fast Blank signal of a SCART connector. FBCOUT 3.3V digital output. A delayed version of the FBCIN signal, aligned with the digital pixel data. RESET Digital 3.3V input, active low, 70k Ω pull-up to VD. Take low for at least 1µs and then high again to reset the ISL51002. This pin is not necessary for normal use and may be tied directly to the VD supply. XTALIN Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. XTALOUT Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. XCLKOUT 3.3V digital output. Buffered crystal clock output at fXTAL or fXTAL/2. May be used as system clock for other system components. SADDR Digital 3.3V input. Address = 0x98 (1001100x) when tied low. Address = 0 x 9A (1001101x) when tied high. SCL Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface. SDA Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface. EXTCLKIN Digital 3.3V input. External clock input for AFE. R[9:0] 3.3V digital output. 10-bit Red channel pixel data. G[9:0] 3.3V digital output. 10-bit Green channel pixel data. B[9:0] 3.3V digital output. 10-bit Blue channel pixel data. DATACLK 3.3V digital output. Data (pixel) clock output. DATACLK 3.3V digital output. Inverse of DATACLK. HSOUT 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals) HSYNCOUT 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or SOGIN. VSYNCOUT 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period. ISL51002 |
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