9

FN6164.3

February 29, 2012

Pin Descriptions

SYMBOL

DESCRIPTION

Analog inputs. Red channels. AC couple through 0.1µF. Do not connect if not used.

Analog inputs. Green channels. AC couple through 0.1µF. Do not connect if not used.

Analog inputs. Blue channels. AC couple through 0.1µF. Do not connect if not used.

Analog inputs. Sync on Green. Connect to corresponding Green channel video source through a 0.01µF capacitor in

series with a 500

Ω resistor.

Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's HSYNC source. For 5V

signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pFcapacitor

Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's VSYNC source. For 5V

signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pF capacitor

Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transitions on

the active channel’s HSYNC/SOG.

Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the

clamp DAC.

Digital 3.3V input. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during VSYNC to allow 2x

Digital 3.3V input.Connect to the Fast Blank signal of a SCART connector.

RESET

Digital 3.3V input, active low, 70k

Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended

Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended

components.

SADDR

Digital 3.3V input. Address = 0x98 (1001100x) when tied low.

Address = 0 x 9A (1001101x) when tied high.

SCL

Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.

SDA

Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.

Digital 3.3V input. External clock input for AFE.

R[9:0]

3.3V digital output. 10-bit Red channel pixel data.

G[9:0]

3.3V digital output. 10-bit Green channel pixel data.

B[9:0]

3.3V digital output. 10-bit Blue channel pixel data.

DATACLK

3.3V digital output. Data (pixel) clock output.

DATACLK

3.3V digital output. Inverse of DATACLK.

3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is

always purely horizontal sync (without any composite sync signals)

3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This

3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the

disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.

ISL51002