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ISL9000AIRMGZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL9000AIRMGZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 13 page ISL9000A 3 FN6391.2 March 26, 2014 Submit Document Feedback Pin Configuration ISL9000A (10 LD 3X3 DFN) TOP VIEW VIN EN1 EN2 CBYP CPOR VO1 VO2 POR2 POR1 GND 2 3 4 1 5 9 8 7 10 6 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1 VIN Analog I/O Supply Voltage/LDO Input: Connect a 1µF, X5R ceramic capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable. 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable. 4 CBYP Analog I/O Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the desired noise and PSRR performance. 5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin: Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01µF). 6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane. 7POR1 Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low): Internally connected to VO1 through 100k Ω resistor. 8POR2 Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low): Internally connected to VO2 through 100k Ω resistor. 9VO2 Analog I/O LDO-2 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). 10 VO1 Analog I/O LDO-1 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). |
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