7

FN9240.1

January 22, 2010

Operation and Adaptive Shoot-Through Protection

Designed for high speed switching, the ISL6596 MOSFET

driver controls both high-side and low-side N-Channel FETs

from one externally provided PWM signal.

A rising transition on PWM initiates the turn-off of the lower

MOSFET (see “Timing Diagram” on page 6). After a short

Specifications” table on page 4. Adaptive shoot-through

circuitry monitors the LGATE voltage and turns on the upper

voltage drops below ~1V. The upper gate drive then begins to

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

monitors the UGATE-PHASE voltage and turns on the lower

turning on the lower MOSFET. These methods prevent both the

lower and upper MOSFETs from conducting simultaneously

(shoot-through), while adapting the dead time to the gate

charge characteristics of the MOSFETs being used.

This driver is optimized for voltage regulators with large step

down ratio. The lower MOSFET is usually sized larger

compared to the upper MOSFET because the lower

MOSFET conducts for a longer time during a switching

period. The lower gate driver is therefore sized much larger

to meet this application requirement. The 0.4

Ω on-resistance

and 4A sink current capability enable the lower gate driver to

absorb the current injected into the lower gate through the

drain-to-gate capacitor of the lower MOSFET and help

prevent shoot through caused by the self turn-on of the lower

MOSFET due to high dV/dt of the switching node.

PWM Input and Threshold Control

A unique feature of the ISL6596 is the programmable PWM

logic threshold set by the control pin (VCTRL) voltage. The

VCTRL pin should connect to the VCC of the controller, thus

the PWM logic threshold follows with the voltage level of the

controller. For 5V applications, this pin can tie to the driver

VCC and simplify the routing.

The ISL6596 also features the adaptable tri-state PWM input.

Once the PWM signal enters the shutdown window, either

MOSFET previously conducting is turned off. If the PWM signal

remains within the shutdown window for longer than the gate

turn-off propagation delay of the previously conducting

MOSFET, the output drivers are disabled and both MOSFET

gates are pulled and held low. The shutdown state is removed

when the PWM signal moves outside the shutdown window.

The PWM rising and falling thresholds outlined in the “Electrical

Specifications” on page 4 determine when the lower and upper

gates are enabled. During normal operation in a typical

application, the PWM rise and fall times through the shutdown

window should not exceed either output’s turn-off propagation

delay plus the MOSFET gate discharge time to ~1V.

Abnormally long PWM signal transition times through the

shutdown window will simply introduce additional dead time

between turn off and turn on of the synchronous bridge’s

MOSFETs. For optimal performance, no more than 50pF

parasitic capacitive load should be present on the PWM line of

ISL6596 (assuming an Intersil PWM controller is used).

Bootstrap Considerations

This driver features an internal bootstrap diode. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit.

Equation 1 helps select a proper bootstrap capacitor size:

control MOSFETs. The

allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.110µF is required. The next larger standard value

capacitance is 0.22µF. A good quality ceramic capacitor is

recommended.

C

BOOT_CAP

Q

GATE

ΔV

BOOT_CAP

--------------------------------------

≥

Q

GATE

Q

G1

VCC

•

V

GS1

-------------------------------

N

Q1

•

=

(EQ. 1)

20nC

ΔV

2.0

1.6

1.4

1.0

0.8

0.6

0.4

0.2

0.0

0.3

0.0

0.1

0.2

0.4

0.5

0.6

0.9

0.7

0.8

1.0

1.2

1.8

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

ISL6596