M2S56D20AKT-75L datasheet(4/37 Pages) MITSUBISHI

Part #	M2S56D20AKT-75L

Description	256M Double Data Rate Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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4

MITSUBISHI ELECTRIC

Jul. '01 Preliminary

MITSUBISHI LSIs

DDR SDRAM (Rev.1.0)

M2S56D20/ 30/ 40AKT

256 M Double Data Rate Synchronous DRAM

Type Designation Code

This rule is applied to only Synchronous DRAM family.

Mitsubishi Main Designation

Speed Grade

10: 125 MHz@CL=2.5,100MHz@CL=2.0

75: 133 MHz@CL=2.5 ,100MHz@CL=2.0

Package Type TP: TSOP(II)

Process Generation

Function Reserved for Future Use

Organization 2

n

2: x4, 3: x8, 4: x16

D DR Synchronous DRAM

Density 56: 256M bits

Interface

V:LVTTL, S:SSTL_3, _2

Memory Style (DRAM)

M

2 S 56

D 3

0 A TP – 75A

BLOCK DIAGRAM

/CS

/RAS /CAS

/ WE

UDM,

LDM

Memory

Array

Bank #0

DQ0 - 15

I/O Buffer

Memory

Array

Bank #1

Memory

Array

Bank #2

Memory

Array

Bank #3

Mode Register

Control Circuitry

Address Buffer

A0-12

BA0,1

Clock Buffer

CLK

CKE

Control Signal Buffer

QS Buffer

UDQS,LDQS

DLL

75 A: 133MHz@CL=2.5, 133MHz@CL=2.0

/CLK

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M2S56D20AKT-75L Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor

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