ISL6146

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FN7667.5

August 17, 2015

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ISL6146B

ISL6146E

EN

Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V

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ISL6146C

OVP

Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET

configuration must be employed to implement the OVP capability. Range: 0V to 24V

5

GND

Chip ground reference.

6FAULT

down this pin to GND as it detects a fault or a disabled input (EN = ‘0’ or EN = ‘1’).

Different types of faults and their detection mechanisms are discussed in more detail on page 17. These faults include:

c. FET G-D or G-S or D-S shorts.

f. Over-Temperature

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ADJ

connected to VOUT or can be connected through a 5kΩ to 100kΩ resistor to GND. Allows for adjusting the voltage difference

threshold to prevent unintended turn-off of the pass FET due to normal system voltage fluctuations.

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VOUT

The second sensing node for external FET control and connected to the Load side (OR-ing MOSFET Drain). This is the

to be turned off. Range: 0V to 24V

PAD

Thermal Pad Connect to GND

MSOP/

DFN

SYMBOL

DESCRIPTION