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ISL6146AFRZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL6146AFRZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 28 page ISL6146 3 FN7667.5 August 17, 2015 Submit Document Feedback Block Diagram Pin Configuration ISL6146 (8 LD MSOP/DFN) TOP VIEW + + VIN VOUT ADJ FLT GATE BIAS 4A 8mA HIGH SPEED COMPARATOR Q-PUMP VDS FORWARD REGULATOR REVERSE DETECTION COMPARATOR ENABLE + FAULT DIAGNOSTIC 1. VIN - VOUT > 570mV 2. GATE - VIN < 220mV (A, B, C only) 3. TEMP > +150°C 4. VBIAS < POR (ISL6146A/B/D/E) 5. VIN OR VOUT < POR (ISL6146C) 19mV 57mV * Connected to BIAS on ISL6146A/B/D/E * Connected to VOUT on ISL6146C ENABLE + - VREF EN/EN ISL6146A/B/D/E + - VREF OVP ISL6146C EN UVLO + + 6. VIN < VOUT 7. Gate to Drain and Gate to Source Shorts ISL6146A, ISL6146B, ISL6146D, ISL6146E ISL6146C VIN GATE FAULT VOUT ADJ EN ISL6146A/D BIAS GND EN ISL6146B/E 1 2 3 4 8 7 6 5 VIN GATE FAULT VOUT ADJ GND UVLO OVP 1 2 3 4 8 7 6 5 EPAD on DFN only, connect to GND Pin Descriptions MSOP/ DFN SYMBOL DESCRIPTION 1 GATE Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically <1ms. Allows active control of external N-Channel FET gate to perform OR-ing function. The GATE drive is between VIN + 7V at VIN = 3.3V and VIN +12V at VIN = 18V. 2 VIN Connected to the sourcing supply side (OR-ing MOSFET source), this pin serves as the sense pin to determine the OR’d supply voltage. The OR-ing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally set threshold or the defaulted internal threshold. Range: 0V to 24V 3 ISL6146A ISL6146B ISL6146D ISL6146E BIAS Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than VIN. Range: 3.0 to 24V 3 ISL6146C UVLO Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V 4 ISL6146A ISL6146D EN Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ. Range: 0V to 24V |
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