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CSD95373AQ5M Datasheet(PDF) 3 Page - Texas Instruments |
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CSD95373AQ5M Datasheet(HTML) 3 Page - Texas Instruments |
3 / 26 page NC NC VDD ENABLE NC VSW PWM TAO FCCM BOOT BOOT_R VIN 1 2 3 4 5 6 7 8 9 10 11 12 PGND 13 CSD95373AQ5M www.ti.com SLPS458A – DECEMBER 2013 – REVISED AUGUST 2014 5 Pin Configuration And Functions PIN DESCRIPTION PIN DESCRIPTION NO. NAME 1, 2, 4 NC No Connect, must leave floating 3 ENABLE Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off and both MOSFET gates are actively pulled low. An internal 100 k Ω pulldown resistor pulls the ENABLE pin LOW if left floating. 5 VDD Supply Voltage to Gate Driver and internal circuitry 6 VSW Phase node connecting the HS MOSFET Source and LS MOSFET Drain - pin connection to the output inductor 7 VIN Input Voltage Pin. Connect input capacitors close to this pin. 8 BOOT_R Return path for HS gate driver, connected to VSW internally 9 BOOT Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R, ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. 10 FCCM This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for Sync FET. When FCCM is HIGH, the device operated in Forced Continuous Conduction Mode. An internal 5 µA current source will pull the FCCM pin to VDD if left floating. 11 TAO/ Temperature amplifier output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in FAULT the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature is reported. TAO is pulled up to 3.3 V if Thermal Shutdown occurs. TAO should be bypassed to PGND with a 1 nF 16 V X7R ceramic capacitor. 12 PWM Pulse width modulated tri-state input from external controller. Logic LOW sets Control FET gate low and Sync FET gate high. Logic HIGH sets Control FET gate high and Sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-State Shutdown Hold-off Time (t3HT) 13 PGND Power Ground Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 |
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