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PSMN9R5-100PS Datasheet(PDF) 6 Page - NXP Semiconductors |
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PSMN9R5-100PS Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 13 page NXP Semiconductors PSMN9R5-100PS N-channel 100 V 9.6 mΩ standard level MOSFET in T0220 PSMN9R5-100PS All information provided in this document is subject to legal disclaimers. © NXP N.V. 2013. All rights reserved Product data sheet 17 October 2013 6 / 13 Symbol Parameter Conditions Min Typ Max Unit Crss reverse transfer capacitance - 185 - pF td(on) turn-on delay time - 22 - ns tr rise time - 25.2 - ns td(off) turn-off delay time - 52.2 - ns tf fall time VDS = 50 V; RL = 0.8 Ω; VGS = 10 V; RG(ext) = 4.7 Ω; Tj = 25 °C - 22.8 - ns Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.85 1.2 V trr reverse recovery time - 61.5 - ns Qr recovered charge IS = 20 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 50 V - 157 - nC 003aae025 6 12 18 24 30 4 8 12 16 20 VGS(V) RDSon (mΩ) Fig. 5. Drain-source on-state resistance as a function of gate-source voltage; typical values. 003aae022 0 2000 4000 6000 8000 0 3 6 9 12 VGS (V) C (pF) Ciss Crss Fig. 6. Input and reverse transfer capacitances as a function of gate-source voltage; typical values |
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