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MXD1005 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MXD1005 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 8 page __________Applications Information Supply and Temperature Effects on Delay Variations in supply voltage may affect the MXD1005’s fixed tap delays. Supply voltages beyond the specified range may result with larger variations. The devices are internally compensated to reduce the effects of temper- ature variations. Although these devices might vary with supply and temperature, the delays vary unilaterally, which suggests that TAP3 can never be faster than TAP2. Capacitance and Loading Effects on Delay The output load can affect the tap delays. Larger capacitances tend to lengthen the rising and falling edges, thus increasing the tap delays. As the taps are loaded with other logic devices, the increased load will increase the tap delays. Board Layout Considerations/Decoupling The device should be driven with a source that can deliver the required current for proper operation. A 0.1µF ceramic bypassing capacitor could be used. The board should be designed to reduce stray capaci- tance. 5-Tap Silicon Delay Line _______________________________________________________________________________________ 5 VIL VIH PERIOD tRISE IN OUT 0.6V 0.6V 2.4V 2.4V 1.5V 1.5V 1.5V 1.5V 1.5V tFALL tWI tPLH tPHL 20% 50 Ω 0.1µF VCC IN (+5V) 20% TIME MEASUREMENT UNIT TAP1 TAP2 TAP3 TAP4 TAP5 74FO4 20% 20% 20% MXD1005 Figure 1. Timing Diagram Figure 2. Test Circuit |
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Similar Description - MXD1005 |
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