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MAX807L Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX807L
Description  Full-Featured uP Supervisory Circuit with /-1.5% Reset Accuracy
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX807L Datasheet(HTML) 4 Page - Maxim Integrated Products

 
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Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
4
_______________________________________________________________________________________
Note 1: Either VCC or VBATT can go to 0 if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX807 from the battery (excluding IOUT) typically goes to 15µA when (VBATT - 0.1V)
< VCC < VBATT. In most applications, this is a brief period as VCC falls through this region (see Typical Operating Characteristics).
Note 3: “+”= battery discharging current, “-”= battery charging current.
Note 4: WDI is internally connected to a voltage-divider between VCC and GND. If unconnected, WDI is driven to 1.8V (typical),
disabling the watchdog function.
Note 5: Overdrive (VOD) is measured from center of hysteresis band.
Note 6: The chip-enable resistance is tested with VCE IN = VCC/2, and ICE IN = 1mA.
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
PFI Leakage Current
±0.005
±40
nA
mV
20
PFI Hysteresis
µA
±0.00002
±1
CE IN Leakage Current
Disabled mode, MR = 0V
µs
14
PFI to PFO Delay (Note 5)
PFI Input Threshold
VPFT
VPFI falling
2.22
2.285
2.35
V
2.20
2.265
2.33
RESET to CE OUT Delay
VCC falling
28
µs
75
150
CE IN to CE OUT Resistance
(Note 6)
Enabled mode, VCC = VRST (max)
MR Minimum Pulse Input
1
µs
ns
170
MR-to-RESET Propagation
Delay
mA
17
CE OUT Short-Circuit Current
(RESET Active)
VCC = 5V, disabled mode,
CE OUT = 0, MR = 0V
ns
28
CE IN to CE OUT
Propagation Delay (Note 7)
VCC = 5V, CLOAD = 50pF,
50
Ω source impedance driver
V
3.5
CE OUT Output Voltage High
(RESET Active)
Disabled mode, MR = 0V
MR Threshold
VIH
2.4
V
BATT OK Threshold
VBOK
2.200
2.265
2.350
V
BATT OK Hysteresis
20
mV
Output Voltage
(PFO, BATT OK)
VOL
ISINK = 3.2mA
0.4
V
Output Short-Circuit Current
ISC
Output sink current
35
mA
VPFI rising
VBATT - 0.1 VBATT
VCC = 5V,
IOUT = 2mA
VCC = 0V,
IOUT = 10µA
VIL
0.8
VOH
ISOURCE = 5mA
VCC - 1.5
Output source current
20
VOD = 30mV, VPFI falling
MR Pullup Current
MR = 0V
50
100
200
µA
CHIP-ENABLE GATING
MANUAL RESET INPUT
BATT OK COMPARATOR
LOGIC OUTPUTS


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