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CMX910 Datasheet(PDF) 1 Page - CML Microcircuits |
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CMX910 Datasheet(HTML) 1 Page - CML Microcircuits |
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1 / 61 page  CMX910 AIS Baseband Processor © 2009 CML Microsystems Plc D/910/6 March 2009 Provisional Issue Features: • Half-Duplex GM(F)SK, FSK and DSC Capabilities • I and Q Radio Interface • Slot/Sample Counter with UTC Timing Interface • Low-Power (3.0 to 3.6V) Operation • Optimum Co-channel and Adjacent-channel Performance • Low Profile, 64-lead LQFP (L9) and Leadless VQFN (Q1) Packages • Flexible Signal Channels – Two Simultaneous Rx – One Tx – Optional FSK Interface • Auxiliary ADC and DAC Functions – 5 x (10-bit) DACs – 5-Input MUX (10-bit) ADC • AIS Data Formatted and Raw Data Modes Applications: • Supports Carrier-Sensing Channel Access (CSTDMA) Operation • Automatic Identification System (AIS) for Marine Safety • RF Device-Enable Facilities • Class A or B AIS Transponders • C-BUS Serial Interface with Expansion Port • AIS Rx-only Modules HDLC/ NRZI decoder Message buffers GMSK/ FSK decoder HDLC/ NRZI encoder Message buffer GMSK/ FSK encoder HDLC/ NRZI decoder Message buffers GMSK/ FSK decoder Aux ADC Aux DACs Device Enable Port FSK Retiming (External) Reset and Power Control Slot and Sample Timer Interrupt Generator C-BUS Interface C-BUS Expansion Port CMX910 RF Rx1: I/Q down- converter Tx: I/Q up- converter Rx2: I/Q down- converter Σ−Δ ADCs Σ−Δ ADCs Σ−Δ DACs Radio Host µC GNSS Engine Other C-BUS Devices Optional FSK Demod. (FX604) TCXO 1. Brief Description A highly integrated Baseband Signalling Processor IC, the CMX910 fulfils the requirements of the class A and class B marine Automatic Identification System (AIS) transponder market. The CMX910 is half duplex in operation, comprising two parallel I+Q Rx paths and one Tx path. These are configurable for AIS or DSC operation. The device performs channel filtering and signal modulation/demodulation with associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing (flags, bit stuffing/de-stuffing, CRC generate/check). An external 1200bps FSK demodulator interface provides a third parallel decode path for DSC, as required by the class A market. Integrated Rx/Tx data buffers and a flexible slot/sample timer are also provided, all of which greatly reduce the processing requirements of the host µC. Provision of a C-BUS expansion port, an RF device enable port and a number of auxiliary ADCs and DACs further simplifies the system hardware design, reducing the overall equipment cost and size. |
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