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5

LS-SERIES

(28V Input, Single/Dual Output)

1.

Parameter is tested as part of design characterization or after design changes. Thereafter, parameter

shall be guaranteed to the limits specified.

2.

Parameter verified during line and load regulation tests.

3.

Output load current must be distributed such that at least 20% of the total load current is being provided by

one of the outputs.

4.

Load current split equally between outputs on dual output models.

5.

Cross regulation is measured with 20% rated load on output under test while changing the load on the

other output from 20% to 80% of rated.

6.

Guaranteed for a D.C. to 20MHz bandwidth. Tested using a 20KHz to 10MHz bandwidth using the circuit

on page 6.

7.

Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. For

a capacitive load in excess of the maximum limit, consult the factory.

8.

90% of nominal.

9.

Load step transition time

≤ 10µs.

its steady state value.

11. Line step transition time

≤ 100µs.

12. Turn-on delay time from either a step application of input power or a logic low to a logic high transition on

13. For operation at temperatures between +85°C and 125°C, de-rate the maximum output power linearly from

100% to 75%.

14. End of life (EOL) is

±3%

Limits

Parameter

Group A

Subgroup

Conditions

-55

unless otherwise specified

Min

Nom

Max

Unit

LS2801R5S

LS2802R5S

LS2803R3S

LS2805S

LS2812S

LS2815S

LS2805D

LS2812D

LS2815D

4,5,6

10% Load, Full Load

Notes 4,12

0

150

250

330

500

1000

1000

500

1000

1000

10

mV

ms

Capacitive Load (CL)

LS2801R5S

LS2802R5S

LS2803R3S

LS2805S

LS2812S

LS2815S

LS2805D

LS2812D

LS2815D

No effect on DC performance

Notes 1, 4, 7

Each output on duals

2500

2500

2200

1000

180

120

500

90

60

µF

Line Rejection

1

DC to 50KHz, Notes 1, 4

35

50

dB

Isolation

1

Input to Output or Any Pin to Case

except pin 3, test @ 500VDC

100

M

Ω

Device Weight

80

g

MTBF

MIL-HDBK-217F2, SF, 35

°C

4.0 x 10

6

Hr