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LDC1101 Datasheet(PDF) 6 Page - Texas Instruments |
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LDC1101 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 54 page  tODZ tth(CS)t SCLK SDO CSB tsu(CS) 1 st Clock 8 th Clock 16 th Clock D7 D1 D0 tOD tOZD ttIAGt twL twH tsu th Valid Data Valid Data SCLK SDI LDC1101 SNOSD01B – MAY 2015 – REVISED JULY 2015 www.ti.com 7.7 Timing Requirements MIN TYP MAX UNIT tSTART Start-up time from shutdown to sleep 0.8 ms Wake-up time (from completion of SPI to conversion start; does not include tWAKE 0.04 ms sensor settling time) INTERFACE TIMING REQUIREMENTS(1) ƒSCLK Serial clock frequency 8 MHz twH SCLK pulse-width high 0.4 / ƒSCLK s twL SCLK pulse-width low 0.4 / ƒSCLK s tsu SDI setup time 10 ns th SDI hold time 10 ns tODZ SDO driven-to-tristate time 25 ns tOZD SDO tristate-to-driven time 25 ns tOD SDO output delay time 20 ns tsu(CS) CSB setup time 20 ns th(CS) CSB hold time 20 ns tIAG CSB inter-access interval 100 ns tw(DRDY) Data ready pulse width 1/ƒSENSOR ns (1) Unless otherwise noted, all limits specified at TA = 25°C, VDD = 1.8 V, 10 pF capacitive load in parallel with a 10 kΩ load on the SDO pin. Specified by design; not production tested. Figure 1. Write Timing Diagram Figure 2. Read Timing Diagram 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LDC1101 |
Similar Part No. - LDC1101_15 |
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