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OPT9221 Datasheet(PDF) 8 Page - Texas Instruments |
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OPT9221 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 104 page  OPT9221 SBAS703A – JUNE 2015 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/O I/O I/O BANK DESCRIPTION STANDARD NAME NO. RSVD D11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD D12 Bidir 1.8 V VCCIO7 Leave unconnected RSVD D15 Bidir 3.3 V VCCIO6 Leave unconnected RSVD D16 Bidir 3.3 V VCCIO6 Leave unconnected RSVD E10 Bidir 1.8 V VCCIO7 Leave unconnected RSVD E11 Bidir 1.8 V VCCIO7 Leave unconnected RSVD F3 Bidir 1.8 V VCCIO1 Leave unconnected RSVD F14 Bidir 3.3 V VCCIO6 Leave unconnected RSVD G1 Bidir 1.8 V VCCIO1 Leave unconnected RSVD G11 Bidir 3.3 V VCCIO6 Leave unconnected RSVD G15 Bidir 3.3 V VCCIO6 Leave unconnected RSVD J1 Output 1.8 V VCCIO2 Reserved RSVD J12 Bidir 2.5 V VCCIO5 Leave unconnected RSVD J13 Bidir 2.5 V VCCIO5 Leave unconnected RSVD J14 Bidir 2.5 V VCCIO5 Leave unconnected RSVD K12 Bidir 2.5 V VCCIO5 Leave unconnected RSVD L13 Bidir 2.5 V VCCIO5 Leave unconnected RSVD L16 Bidir 2.5 V VCCIO5 Leave unconnected RSVD M6 Bidir 1.8 V VCCIO3 Leave unconnected RSVD N14 Bidir 2.5 V VCCIO5 Leave unconnected RSVD P15 Bidir 2.5 V VCCIO5 Leave unconnected RSVD_IN A8 Input 1.8 V VCCIO8 Tie to GND RSVD_IN A9 Input 1.8 V VCCIO7 Tie to GND RSVD_IN B8 Input 1.8 V VCCIO8 Tie to GND RSVD_IN B9 Input 1.8 V VCCIO7 Tie to GND RSVD_IN L14 Input Analog VCCIO5 Tie to 2.5 V RSVD_IN L15 Input Analog VCCIO5 Tie to 2.5 V RSVD_IN M2 Input 1.8 V VCCIO2 Tie to GND RSVD_IN R8 Input 1.8 V VCCIO3 Tie to GND RSVD_IN R9 Input 1.8 V VCCIO4 Tie to GND RSVD_IN T8 Input 1.8 V VCCIO3 Tie to GND RSVD_IN T9 Input 1.8 V VCCIO4 Tie to GND SENSOR_CLK B14 Output 1.8 V VCCIO7 Sensor main clock SENSOR_DEMOD_CL A14 Output 1.8 V VCCIO7 Demod clock for test K SENSOR_RSTZ D14 Output 1.8 V VCCIO7 Sensor reset SLEEP B1 Input 1.8 V VCCIO1 Puts the TFC in standby mode when enabled SYSCLK_IN E1 Input 1.8 V VCCIO1 Main system clock input TIC_C H3 Input 2.5 V – Reserved. Needs external pull-down resistor of 10 k Ω If high, TFC releases the control of configuration pins. In TIC_CEZ J3 Input 1.8 V VCCIO1 slave boot modes, tie to ground. TIC_CLK H1 Input 1.8 V VCCIO1 Configuration data clock TIC_CONFIGZ H5 Input 1.8 V VCCIO1 Used to start firmware load operation TIC_CONF_DONE H14 Output Open Drain VCCIO6 Used to indicate end of firmware load operation In master serial boot mode, Used by TFC to load TIC_CSOZ D2 Output 1.8 V VCCIO1 firmware from EEPROM as chip select pin. TIC_DATA_0 H2 Input 1.8 V VCCIO1 Configuration data pin 0 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: OPT9221 |
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