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MAX6950CEE Datasheet(PDF) 3 Page - Maxim Integrated Products

Part No. MAX6950CEE
Description  Serially Interfaced, 2.7V to 5.5V, 5- and 8-Digit LED Display Drivers
Download  19 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX6950CEE Datasheet(HTML) 3 Page - Maxim Integrated Products

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Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Slow Segment Blink Period
(Internal Oscillator)
fSLOWBLINK
Eight digits scanned, OSC = RC oscillator,
RSET = 56k
Ω, CSET = 27pF
1s
Fast Segment Blink Period
(Internal Oscillator)
fFASTBLINK
Eight digits scanned, OSC = RC oscillator,
RSET = 56k
Ω, CSET = 27pF
0.5
s
Fast or Slow Segment Blink Duty
Cycle (Note 2)
49.9
50
50.1
%
Digit Drive Sink Current
IDIGIT
TA = +25°C, VLED = 2.4V
240
320
400
mA
Segment Drive Source Current
ISEG
TA = +25°C, VLED = 2.4V
-30
-40
-50
mA
Digit Drive Sink Current (Note 2)
IDIGIT
TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V
80
mA
Segment Drive Source Current
(Note 2)
ISEG
TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V
-10
mA
Slew Rate Rise Time
∆ISEG/∆t
TA = +25°C
35
mA/µs
LOGIC INPUTS
Input Current DIN, CLK, CS
IIH, IIL
VIN = 0 or V+
-2
2
µA
Logic High Input Voltage DIN,
CLK, CS
VIH
2.4
V
Logic Low Input Voltage DIN,
CLK, CS
VIL
0.4
V
Hysteresis Voltage DIN, CLK, CS
∆VI
0.5
V
TIMING CHARACTERISTICS (Figure 1)
CLK Clock Period
tCP
38.4
ns
CLK Pulse Width High
tCH
19
ns
CLK Pulse Width Low
tCL
19
ns
CS Fall to CLK Rise Setup TimetCSS
9.5
ns
CLK Rise to CS Rise Hold Time
tCSH
3ns
DIN Setup Time
tDS
9.5
ns
DIN Hold Time
tDH
0ns
CS Pulse High
tCSW
19
ns
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)
CLK Clock Period
tCP
50
ns
CLK Pulse Width High
tCH
24
ns
CLK Pulse Width Low
tCL
24
ns
CS Fall to CLK Rise Setup Time
tCSS
12
ns
CLK Rise to CS Rise Hold Time
tCSH
4ns
DIN Setup Time
tDS
12
ns
DIN Hold Time
tDH
4ns
CS Pulse High
tCSW
24
ns
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.


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