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AFE5812 Datasheet(PDF) 49 Page - Texas Instruments

Part # AFE5812
Description  AFE5812 Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, and Digital I/Q Demodulator, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 180 mW/CH
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE5812 Datasheet(HTML) 49 Page - Texas Instruments

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A7
A6
A5
A4
A3
A2
A1
A0
SEN
SCLK
SDATA
SDOUT
Start Sequence
End Sequence
t
7
t
6
t
2
t
4
t
1
t
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D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
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D1
D0
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AFE5812
www.ti.com
SLOS816A – MARCH 2015 – REVISED MARCH 2015
Programming (continued)
Figure 85. Serial Interface Register Read
The AFE5812 SDOUT buffer is tri-stated and gets enabled only when 0[1] (REGISTER READOUT ENABLE) is
enabled. SDOUT pins from multiple AFE5812s can be tied together without any pullup resistors. Level shifter
SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.
10.5.1.3 SPI for Demodulator
Demodulator is enabled after a software or hardware reset. It can be disabled by setting the LSB of register 0x16
as 1. This is done using the ADC SPI interface, that is, SPI_DIG_EN = 1. The demodulator SPI interface is
independent from the ADC/VCA SPI interface as shown in Figure 83.
To access the specific demodulator registers:
1. SPI_DIG_EN pin is required to be set as 0 during SPI transactions to demodulator registers. Meanwhile,
ADC SEN needs to be set as 0 during demodulator SPI programming.
2. The SPI register address is 8 bits and is made of 2 subchip select bits and 6 register address bits. SPI
register data is 16 bits.
3. ADC CLK and DVDD_LDO1/2 are required to access the demodulation registers.
Table 3. Register Address Bit Description
Bit7
Bit6
Bit 5:0
SCID1_SEL
SCID0_SEL
Register address <5:0>
spacer
4. SCID0_SEL enables configuration of channels 1 through 4. SCID1_SEL enables configuration of channels 5
through 7. When performing demodulator SPI write transactions, these SCID bits can be individually or
mutually used with a specific register address.
5. Register configuration is normally shared by both subchips (both SCID bits should be set as 1). An exception
to this rule would be the DC OFFSET registers (0x14 through 0x17) for which specific channel access is
expected.
Copyright © 2015, Texas Instruments Incorporated
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