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AFE5812 Datasheet(PDF) 35 Page - Texas Instruments |
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AFE5812 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 109 page  2 16 p 1 T 16 1 T 16 10 2 20log p ( ) ( ) ( ) ( ) ( ) ( ) ( ) 0 d 0 0 0 0 d 0 d Vi(t) sin t t t 4 1 1 LO(t) sin t sin 3 t sin 5 t ... 3 5 2 Vo(t) cos t cos 2 t t ... = w + w + j + w é ù = w + w + w ê ú p ë û é ù = w + f - w - w + f ë û p f Vi(t) Vo(t) LO(t) AFE5812 www.ti.com SLOS816A – MARCH 2015 – REVISED MARCH 2015 Figure 68. Block Diagram of Mixer Operation (1) From Equation 1, the third-order and fifth-order harmonics from the LO can interface with the third-order and fifth- order harmonic signals in the Vi(t), or the noise around the third-order and fifth-order harmonics in the Vi(t). Therefore, the mixer’s performance is degraded. To eliminate this side effect due to the square-wave demodulation, a proprietary harmonic-suppression circuit is implemented in the AFE5812. The third- and fifth- harmonic components from the LO can be suppressed by over 12 dB. Thus, the LNA output noise around the third-order and fifth-order harmonic bands is not down-converted to base band. Hence, the device achieves better noise figure. The conversion loss of the mixer is about –4 dB, which is derived from . The mixed current outputs of the eight channels are summed together internally. An internal low-noise operational amplifier is used to convert the summed current to a voltage output. The internal summing amplifier is designed to accomplish low-power consumption, low noise, and ease of use. CW outputs from multiple AFE5812s can be further combined on system board to implement a CW beamformer with more than eight channels. See Typical Application for more detailed information. Multiple clock options are supported in the AFE5812 CW path. Two CW clock inputs are required: N × ƒcw clock and 1 × ƒcw clock, where ƒcw is the CW transmitting frequency and N could be 16, 8, 4, or 1. Users have the flexibility to select the most convenient system clock solution for the AFE5812. In the 16 × ƒcw and 8 × ƒcw modes, the third- and fifth-harmonic suppression feature can be supported. Thus, the 16 × ƒcw and 8 × ƒcw modes achieve better performance than the 4 × ƒcw and 1 × ƒcw modes. 10.3.5.1 16 × ƒcw Mode The 16 × ƒcw mode achieves the best phase accuracy compared to other modes. It is the default mode for CW operation. In this mode, 16 × ƒcw and 1 × ƒcw clocks are required. 16 × ƒcw generates LO signals with 16 accurate phases. Multiple AFE5812s can be synchronized by the 1 × ƒcw , that is LO signals in multiple AFEs can have the same starting phase. The phase noise specification is critical only for 16× clock. The 1× clock is for synchronization only and does not require low phase noise. See the phase noise requirement in Typical Application. Figure 69 shows the top-level clock distribution diagram. Each mixer's clock is distributed through a 16 × 8 cross- point switch. The inputs of the cross-point switch are 16 different phases of the 1× clock. TI recommends to align the rising edges of the 1 × ƒcw and 16 × ƒcw clocks. The cross-point switch distributes the clocks with appropriate phase delay to each mixer. For example, Vi(t) is a received signal with a delay of , a delayed LO(t) should be applied to the mixer to compensate for the delay. Thus a 22.5 ⁰ delayed clock, that is , is selected for this channel. The mathematic calculation is expressed in the following equations: Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: AFE5812 |
Similar Part No. - AFE5812_15 |
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Similar Description - AFE5812_15 |
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