UCC28632D datasheet(7/79 Pages) TI

Part #	UCC28632D

Description	High-Power Flyback Controller with Primary-Side Regulation and Peak-Power Mode

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Manufacturer	TI [Texas Instruments]

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UCC28630

UCC28631

UCC28632, UCC28633

www.ti.com

SLUSBW3C – MARCH 2014 – REVISED MARCH 2015

8.5 Electrical Characteristics

over operating junction temperature range (unless otherwise noted) and VDD = 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

START-UP CURRENT SOURCE

VDD pin short-circuit charging

IVDD0

VDD = 0.2 V, VHV = 100 V

0.6

0.9

1.2

mA

current

IVDD1

VDD pin final charging current

VDD = 11.9 V, VHV = 100 V

1.1

4.0

7.6

mA

VDD = 18 V, VHV = 100 V HV,

ILEAK

HV current source leakage current

0.1

0.5

μA

current source off, TA = 25°C

SUPPLY VOLTAGE MONITORING

VDD(start)

VDD start-up voltage

VDD increasing

13.00

14.75

16.50

V

VDD minimum operating voltage

VDD(stop)

VDD decreasing after start-up

7.3

8.0

8.5

V

after start-up

VDD(hyst)

VDD start – VDD stop level

6.5

V

VDD(reset)

VDD reset restart level

3.5

5.0

6.5

V

VDD(ovp)

VDD over-voltage protection level

VDD increasing after start-up

16.5

17.5

18.3

V

Supply current during normal

VSENSE = 0.45 V, CS = 0 V See

(1)

IDD(run)

6.0

9.0

13.0

mA

operation

CLOAD = 700 pF on DRV

Supply current during sleep mode,

VSENSE = 8.0 V, VCS = 1.0 V, light-

IDD(sleep)

90

110

μA

between switching pulses

load mode at 200 Hz, TA = 25°C

OSCILLATOR

fSW(max)

Maximum switching frequency

VSENSE = 0.45 V, VCS = 0 V

110

120

130

kHz

VSENSE = 8.0 V, VCS = 1.0 V, light-

fSW(min)

Minimum switching frequency

0.18

0.20

0.22

kHz

load mode

DMAX

Maximum Duty Cycle

VSENSE = 0.45 V, VCS = 0 V

70%

VSENSE = 8.0 V, VCS = 1.0 V, light-

tON(min)

Minimum On time

550

600

650

ns

load mode

fSW(dith)

Frequency dither range

Except UCC28632

± 6.7%

tDITH

Dither repetition period

Except UCC28632

6.0

ms

SHUTDOWN (SD) PIN (EXTERNAL FAULT INPUT)(2)

IPULLUP

Internal pull-up current source

See (2), (3), (4)

185

210

235

µA

VTRIP(rise)

Fault ok level (rising)

See (2), (3), (4)

3.2

3.5

3.8

V

VTRIP(fall)

Fault trip level (falling)

See (2), (3), (4)

1.7

2.00

2.3

V

VTRIP(hyst)

See (2), (3), (4)

1.5

V

VWAKE(rise)

Wake-up level (rising)

See (2), (3), (4)Except UCC28633

1.8

2.2

2.6

V

tWAKE

Wake delay time

Delay to first DRV pulse

10

µs

(1)

CLOAD = 700 pF included on DRV pin.

(2)

The SD pin functions as an NTC input pin (with internal pull-up) during normal operation. The internal pull-up is clamped to 4 V. At start-

up, the external temperature sensor (NTC) must be cool enough that the SD pin pulls up above the VTRIP(rise) start level. After start-up, if

this pin is pulled below VTRIP(fall) level, this activates external over-temperature shut-down.

(3)

During low power modes (when FSW < FSMP(max)), the internal SD pin pull-up is disabled, and the pin functions as a transient wake-up

input. In this case, if the pin is raised above VWAKE(rise) level, the device wakes from low power sleep mode (rather than waiting for the

scheduled timer-based wake). This is useful for applications that require a response to load transients from zero or near-zero load,

where a wake-up signal can be appropriately coupled to the SD pin from the secondary-side.

(4)

A decoupling capacitor on the SD pin should not be required; if used, it must not exceed 1 nF.

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