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MAX6365 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX6365
Description  SOT23, Low-Power μP Supervisory Circuits with Battery Backup and Chip-Enable Gating
Download  15 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX6365 Datasheet(HTML) 4 Page - Maxim Integrated Products

 
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SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
4
_______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
8
10
9
12
11
15
14
13
16
-40
0
-20
20
40
60
80
SUPPLY CURRENT
vs. TEMPERATURE (NO LOAD)
TEMPERATURE (°C)
VCC = 5.0V
VBATT = 0
0
0.2
0.6
0.4
0.8
1.0
1.2
BATTERY SUPPLY CURRENT
(BACKUP MODE) vs. TEMPERATURE
TEMPERATURE (
°C)
-40
20
40
-20
0
60
80
VBATT = 2.0V
VCC = 0
VBATT = 2.8V
0
2
1
4
3
7
6
5
8
-40
0
-20
20
40
60
80
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
TEMPERATURE (°C)
VBATT = 5.0V
VBATT = 2.0V
VBATT = 2.8V
IOUT = 25mA
VCC = 0
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +5.5V, VBATT = +3.0V, CE IN = VCC, reset not asserted, TA = -40°C to +85°C. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET IN (MAX6368 only)
RESET IN Threshold
VRTH
1.185
1.235
1.285
V
RESET IN Leakage Current
±0.01
±25
nA
RESET IN to Reset Delay
VOD = 50mV, RESET IN falling
1.5
µs
CHIP-ENABLE GATING
CE IN Leakage Current
Reset asserted
±1
µA
CE IN to CE OUT Resistance
Reset not asserted (Note 4)
20
100
CE OUT Short-Circuit Current
Reset asserted, CE OUT = 0
0.75
2.0
mA
VCC = 4.75V
1.5
7
CE IN to CE OUT Propagation
Delay
50
Ω source,
CLOAD = 50pF
VCC = 3.15V
2
9
ns
VCC = 5V, VCC > VBATT, ISOURCE = 100µA
0.8 VCC
CE OUT Output Voltage High
VCC = 0, VBATT > 2.2V, ISOURCE = 1µA
VBATT -
0.1
V
Reset-to-CE OUT Delay
12
µs
Note 1: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: VBATT can be 0 anytime, or VCC can go down to 0 if VBATT is active (except at startup).
Note 3: RESET is pulled up to OUT. Specifications apply for OUT = VCC or OUT = BATT.
Note 4: The chip-enable resistance is tested with VCC = VTH(MAX) and CE IN = VCC/2.


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