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S1003 Datasheet(PDF) 31 Page - Seiko Instruments Inc |
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S1003 Datasheet(HTML) 31 Page - Seiko Instruments Inc |
31 / 42 page MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR Rev.1.0_00 S-1003 Series Seiko Instruments Inc. 31 VIH *1 Input voltage VIL *2 VDD *3 tPHL tPLH 1 μs 1 μs VDD *3 × 10% VDD *3 × 90% Output voltage *1. VIH = 10 V *2. VIL = 0.95 V *3. CMOS output product: VDD Nch open-drain product: VDD1 V R *1 100 k Ω COUT VDD V CD VDD1 *1 VDD OUT VSS + + MR *2 *1. R and VDD1 are unnecessary for CMOS output product. *2. Set to VDD or GND (MR pin non-active). Figure 34 Test Condition of Response Time Figure 35 Test Circuit of Response Time Caution 1. The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 2. When the CD pin is open, a double pulse may appear at release. To avoid the double pulse, attach a 100 pF or more capacitor to the CD pin. Response time when detecting (tPHL) is not affected by CD pin capacitance. Besides, response time when releasing (tPLH) can set the delay time by attaching the CD pin. Refer to "11. Delay time (tD) vs. CD pin capacitance (CD) (Without output pin capacitance)" for details. 11. Delay time (tD) vs. CD pin capacitance (CD) (Without output pin capacitance) S-1003NA12 Ta = +25°C 0.01 0.1 1 10 100 0.01 10000 1000 1000 100 10 1 0.1 CD [nF] S-1003NA24 Ta = +25°C 0.01 0.1 1 10 100 0.01 10000 1000 1000 100 10 1 0.1 CD [nF] S-1003NA50 Ta = +25°C 0.01 0.1 1 10 100 0.01 10000 1000 1000 100 10 1 0.1 CD [nF] |
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