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S1003 Datasheet(PDF) 24 Page - Seiko Instruments Inc

Part No. S1003
Description  MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
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Maker  SII [Seiko Instruments Inc]
Homepage  http://www.sii.co.jp
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S1003 Datasheet(HTML) 24 Page - Seiko Instruments Inc

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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
Seiko Instruments Inc.
24
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B
− the voltage at point A = VHYS in "Figure 17 Operation 2"). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Delay time (tD)
The delay time in the S-1003 Series is a period from the input voltage to the VDD pin exceeding the release voltage
(
+VDET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (CD).
tD
VDD
OUT
+VDET
Figure 31 Delay Time
5. Feed-through current
Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage
detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.
6. Oscillation
In applications where a resistor is connected to the voltage detector input (Figure 32), taking a CMOS active "L"
product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)
causes a voltage drop equal to [feed-through current]
× [input resistance] across the resistor. When the input
voltage drops below the detection voltage (
−VDET) as a result, the output voltage goes to "L". In this status, the
feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The
feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces
oscillation.
(CMOS output product)
RA
VIN
GND
VDD
RB
VDD
CD
VSS
OUT
MR
Figure 32 Example for Bad Implementation Due to Detection Voltage Change


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