CC3100

SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015

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4.11.2.3 Wakeup from Hibernate

Figure 4-8 shows the timing diagram for wakeup from the hibernate state.

Figure 4-8. nHIB Timing Diagram

NOTE

The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate in response to

nHIB being pulled low.

Table 4-4 describes the timing requirements for nHIB.

Table 4-4. nHIB Timing Requirements

Item

Name

Description

Min

Typ

Max

Minimum hibernate

Minimum pulse width

10 ms

time

Hardware wakeup

50 ms

time plus firmware

initialization time

(1)

Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so

on).

(2)

If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.

4.11.3 Clock Specifications

The CC3100 device requires two separate clocks for its operation:

•

A slow clock running at 32.768 kHz is used for the RTC.

•

A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of cheaper crystals rather than dedicated TCXOs for

these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and reduce

overall cost.

16

Specifications

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