ADC12D1600CCMPR datasheet(50/67 Pages) TI

Part #	ADC12D1600CCMPR

Description	12-Bit, Single or Dual, 3200/1600/800 MSPS RF Sampling ADC

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CLK+

CLK-

ADC12D1600/1000RF

Ccouple

ADC12D1600/1000RF

VIN+

50:

Source

VIN-

1:2 Balun

Ccouple

100:

ADC12D1600QML

SNAS615 – DECMEBER 2012

www.ti.com

The analog inputs for the ADC12D1600 are internally buffered, which simplifies the task of driving these inputs

and the RC pole which is generally used at sampling ADC inputs is not required. If the user desires to place an

amplifier circuit before the ADC, care should be taken to choose an amplifier with adequate noise and distortion

performance, and adequate gain at the frequencies used for the application.

Single-Ended Input Signals

The analog inputs of the ADC12D1600 are not designed to accept single-ended signals. The best way to handle

single-ended signals is to first convert them to differential signals before presenting them to the ADC. The easiest

way to accomplish single-ended to differential signal conversion is with an appropriate balun-transformer, as

shown in Figure 49.

Figure 49. Single-Ended to Differential Conversion Using a Balun

When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of the

analog source should be matched to the ADC12D1600's on-chip 100

Ω differential input termination resistor. The

range of this termination resistor is specified as RIN in Converter Electrical Characteristics – Analog Input/Output

and Reference Characteristics.

THE CLOCK INPUTS

The ADC12D1600 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-coupled,

differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with LVDS,

PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100

Ω differential and self-biased.

This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.

CLK Coupling

The clock inputs of the ADC12D1600 must be capacitively coupled to the clock pins as indicated in Figure 50.

Figure 50. Differential Input Clock Connection

The choice of capacitor value will depend on the clock frequency, capacitor component characteristics and other

system economic factors. For example, on the ADC12D1600QML RB, the capacitors have the value Ccouple = 4.7

nF which yields a highpass cutoff frequency, fc = 677.2 kHz.

CLK Frequency

Although the ADC12D1600 is tested and its performance is specified with a differential 1.6 GHz sampling clock, it

will typically function well over the input clock frequency range; see fCLK(min) and fCLK(max) in Converter

Electrical Characteristics – AC Electrical Characteristics. Operation up to fCLK(max) is possible if the maximum

ambient temperatures indicated are not exceeded. Operating at sample rates above fCLK(max) for the maximum

ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that

higher sample rates results in higher power consumption and die temperatures. If in Non-LSPSM and fCLK < 300

MHz, enable LFS in the Control Register (Addr: 0h, Bit 8). In LSPSM, this register bit is already enabled.

50

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