When daisy-chaining MAX536s, the delay from CS

or

equation:

ln

connected.

Additionally, when daisy-chaining devices, the maximum

clock frequency is limited to:

1

Ω and C = 30pF), the maximum clock frequency is

8.7MHz.

Figure 9 shows an alternate method of connecting several

MAX536/MAX537s. In this configuration, the data bus is

common to all devices; data is not shifted through a

daisy-chain. More I/O lines are required in this configu-

ration because a dedicated chip-select input (CS) is

required for each IC.

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

16

______________________________________________________________________________________

Table 1. Serial-Interface Programming Commands

“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,

the DAC registers are latched.

Mode 0, DOUT clocked out on SCK’s falling edge. All DACs

updated from their respective input registers.

Mode 1 (default condition at power-up), DOUT clocked out on

SCK’s rising edge. All DACs updated from their respective

input registers.

Load DAC D input register; DAC D is immediately updated.

0

12-bit DAC data

1

X

1

1

Load DAC C input register; DAC C is immediately updated.

0

12-bit DAC data

1

X

0

1

Load DAC B input register; DAC B is immediately updated.

0

12-bit DAC data

1

X

1

0

Load DAC A input register; DAC A is immediately updated.

0

12-bit DAC data

1

0

X

0

X

XXXXXXXXXXXX

0

1

0

1

X

XXXXXXXXXXXX

0

1

1

1

Update all DACs from their respective input registers.

1

XXXXXXXXXXXX

0

1

X

0

No operation (NOP)

X

XXXXXXXXXXXX

0

0

1

X

Load all DACs from shift register.

X

12-bit DAC data

0

0

0

X

Load input register D; all DAC registers updated.

1

12-bit DAC data

1

1

1

1

Load input register C; all DAC registers updated.

1

12-bit DAC data

1

1

0

1

Load input register B; all DAC registers updated.

1

12-bit DAC data

1

1

1

0

Load input register A; all DAC registers updated.

1

12-bit DAC data

1

1

0

0

Load DAC D input register; DAC output unchanged.

1

12-bit DAC data

1

0

1

1

Load DAC C input register; DAC output unchanged.

1

12-bit DAC data

1

0

0

1

Load DAC B input register; DAC output unchanged.

1

12-bit DAC data

1

0

1

0

Load DAC A input register; DAC output unchanged.

1

12-bit DAC data

1

0

0

0

D11…D0

C0

C1

A0

A1

FUNCTION

LDAC

16-BIT SERIAL WORD

(

)

[

]