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8T49N286 Datasheet(PDF) 24 Page - Integrated Device Technology |
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8T49N286 Datasheet(HTML) 24 Page - Integrated Device Technology |
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24 / 78 page  8T49N286 DATA SHEET FEMTOCLOCK® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 24 REVISION 5 07/08/15 NOTE 1: Settings other than “00” may result in a significant increase in initial lock time. SLEW0[1:0] R/W 00b Phase-slope control for Digital PLL0: 00 = no limit - controlled by loop bandwidth of Digital PLL0, NOTE1. 01 = 83 µsec/sec 10 = 13 µsec/sec 11 = Reserved HOLD0[1:0] R/W 00b Holdover Averaging mode selection for Digital PLL0: 00 = Instantaneous mode - uses historical value 100ms prior to entering holdover 01 = Fast Average Mode 10 = Reserved 11 = Set VCO control voltage to VCC/2 HOLDAVG0 R/W 0b Holdover Averaging Enable for Digital PLL0: 0 = Holdover averaging disabled 1 = Holdover averaging enabled as defined in HOLD0[1:0] FASTLCK0 R/W 0b Enables Fast Lock operation for Digital PLL0: 0 = Normal locking using LCKBW0 & LCKDAMP0 fields in all cases 1 = Fast Lock mode using ACQBW0 & ACQDAMP0 when not phase locked and LCKBW0 & LCKDAMP0 once phase locked LOCK0[7:0] R/W 3Fh Lock window size for Digital PLL0. Unsigned 2’s complement binary number in steps of 2.5ns, giving a total range of 640ns. Do not program to 0. DSM_INT0[8:0] R/W 02Dh Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This implies that for crystal frequencies lower than 16MHz, the doubler circuit must be enabled. DSMFRAC0[20:0] R/W 000000h Fractional portion of Delta-Sigma Modulator value. Divide this number by 221 to determine the actual fraction. DSM_ORD0[1:0] R/W 11b Delta-Sigma Modulator Order for Digital PLL0: 00 = Delta-Sigma Modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation DCXOGAIN0[1:0] R/W 01b Multiplier applied to instantaneous frequency error before it is applied to the Digitally Controlled Oscillator in Digital PLL0: 00 = 0.5 01 = 1 10 = 2 11 = 4 DITHGAIN0[2:0] R/W 000b Dither Gain setting for Digital PLL0: 000 = no dither 001 = Least Significant Bit (LSB) only 010 = 2 LSBs 011 = 4 LSBs 100 = 8 LSBs 101 = 16 LSBs 110 = 32 LSBs 111 = 64 LSBs Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Digital PLL0 Feedback Configuration Register Block Field Descriptions Bit Field Name Field Type Default Value Description |
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