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5P49V5944 Datasheet(PDF) 1 Page - Integrated Device Technology |
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5P49V5944 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 32 page DATASHEET 5P49V5944 REVISION A 07/20/15 1 ©2015 Integrated Device Technology, Inc. Programmable Clock Generator 5P49V5944 Description The 5P49V5944 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is IDTs fifth generation of programmable clock technology (VersaClock® 5). The frequencies are generated from a single reference clock. The input reference can be either a crystal or an LVCMOS reference clock. Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I2C addresses to allow multiple devices to be used in a system. Pin Assignment Features • Generates up to two independent output frequencies • High performance, low phase noise PLL, <0.7 ps RMS typical phase jitter on outputs: – PCIe Gen1, 2, 3 compliant clock capability – USB 3.0 compliant clock capability – 1 GbE and 10 GbE • Two fractional output dividers (FODs) • Independent Spread Spectrum capability on each output pair • Four banks of internal non-volatile in-system programmable or factory programmable OTP memory • I2C serial programming interface • One reference LVCMOS output clock • Two universal output pairs: – Each configurable as one differential output pair or two LVCMOS outputs • I/O Standards: – Single-ended I/Os: 1.8V to 3.3V LVCMOS – Differential I/Os - LVPECL, LVDS and HCSL • Input frequency ranges: – LVCMOS Reference Clock Input (XIN/REF) – 1MHz to 200MHz – Crystal frequency range: 8MHz to 40MHz • Output frequency ranges: – LVCMOS Clock Outputs – 1MHz to 200MHz – LVDS, LVPECL, HCSL Differential Clock Outputs – 1MHz to 350MHz • Individually selectable output voltage (1.8V, 2.5V, 3.3V) for each output pair • Programmable loop bandwidth • Programmable output to output skew • Programmable slew rate control • Programmable crystal load capacitance • Individual output enable/disable • Power-down mode • 1.8V, 2.5V or 3.3V core VDDD, VDDA • Available in 20-pin VFQFPN 3mm x 3mm package • -40° to +85°C industrial temperature operation 1 6 20-pin VFQFPN XOUT OUT1 XIN/REF OUT1B VDDO1 VDDA SD/OE EPAD 2 3 4 5 7 8 910 11 12 13 14 15 16 17 18 19 20 GND GND GND |
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