1

July 1, 2013

IDT82V3911

Short Form

Datasheet

2013 Integrated Device Technology, Inc.

DSC-7238/-

Synchronous Ethernet Two-Channel

PLL for 10GbE and 40GbE

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

FEATURES

HIGHLIGHTS

•

Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter

requirements of leading PHYs supporting 10GBASE-R, 10GBASE-

W, 40GBASE-R, OC-192 and STM-64

•

Supports ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)

compliant equipment

•

Supports clock generation for IEEE-1588 applications

•

Generates SyncE interface clocks (1GE, 10GE, and 40GE)

MAIN FEATURES

•

Provides an integrated solution for reference switching, frequency

translation and jitter attenuation for SyncE and SONET/SDH inter-

faces

•

Integrates 2 DPLLs, one for the transmit path and one for the

receive path

•

Selectable DPLL bandwidth: 18 Hz and 35 Hz

•

Integrates 2 jitter attenuating APLLs to generate ultra-low jitter

clocks

• Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-

PHY

• Supports up to two crystal connections, allowing each APLL to

support up to two modes of operation

•

Supports input and output clocks covering a wide range of frequen-

cies

• Provides IN3, IN4, IN7,IN6 input CMOS clocks whose frequen-

cies range from 2 kHz to 156.25 MHz

• Provides IN1 and IN2 input differential clocks whose frequencies

range from 2 kHz to 625 MHz

• Provides OUT1 to OUT5 output CMOS clocks whose frequency

range from 1PPS to 125 MHz

• Provides OUT6~OUT9 output differential clocks whose fre-

quency range from 25 MHz to 644.53125 MHz

•

Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,

and a 1PPS, 2 kHz or 8 kHz frame sync output signal

•

Supports Forced or Automatic operating mode switch controlled by

an internal state machine. Automatic mode switch supports Free-

Run, Locked and Holdover modes

•

Supports manual and automatic selected input clock switch

•

Supports automatic hitless selected input clock switch on clock fail-

ure

•

Supports three types of input clock sources: recovered clock from

STM-N or OC-n, PDH network synchronization timing and external

synchronization reference timing

•

Supports LVPECL/LVDS and CMOS input/output technologies

•

Supports master clock calibration

•

Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,

ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-

mendations

OTHER FEATURES

•

I2C Microprocessor interface

•

IEEE 1149.1 JTAG Boundary Scan

•

Single 3.3 V operation with 5 V tolerant CMOS I/Os

•

1mm ball pitch CABGA green package

APPLICATIONS

•

Core and access IP switches / routers

•

Gigabit and Terabit IP switches / routers

•

Central Office Timing Source and Distribution

•

DWDM cross-connect and transmission equipment

•

IP core routers and access equipment

•

Cellular and WLL base-station node clocks

•

Broadband and multi-service access equipment