DATA SHEET

ICS87004AGI REVISION D JANUARY 4, 2010

1

©2009 Integrated Device Technology, Inc.

1:4, Differential-to-LVCMOS/LVTTL

Zero Delay Clock Generator

ICS87004I

General Description

The ICS87004I is a highly versatile 1:4 Differential-

to-LVCMOS/LVTTL Clock Generator. The ICS87004I

has two selectable clock inputs. The CLK0, nCLK0

and CLK1, nCLK1 pairs can accept most standard

differential input levels. Internal bias on the nCLK0 and

nCLK1 inputs allows the CLK0 and CLK1 inputs to accept

LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can

be configured as a zero delay buffer, multiplier or divider and has an

input and output frequency range of 15.625MHz to 250MHz. The

reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the input

clock and the output clocks. The PLL_SEL pin can be used to

bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

Features

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

levels on CLK0 and CLK1 inputs

configurable frequencies

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

packages

HiPerClockS™

ICS

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

GND

Q0

SEL0

SEL1

SEL2

SEL3

CLK_SEL

CLK0

nCLK0

GND

Q1

GND

Q2

Q3

MR

FB_IN

PLL_SEL

CLK1

nCLK1

ICS87004I

24-Lead TSSOP

7.8mm x 4.4mm x 0.925mm package body

G Package

Top View

Block Diagram

0

1

Q0

Q1

Q2

Q3

PLL_SEL

FB_IN

SEL0

SEL1

SEL2

SEL3

MR

CLK0

nCLK0

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

÷2, ÷4, ÷8, ÷16

÷32, ÷64, ÷128

Pullup/Pulldown

Pulldown

Pulldown

Pulldown

CLK1

Pulldown

Pullup

Pulldown

Pulldown

Pulldown

Pulldown

0

1

Pin Assignment