MAX5100 datasheet(3/8 Pages) MAXIM

Part #	MAX5100

Description	2.7V to 5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________

3

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.

Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex,

and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF · 240 / 256).

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.

Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at VDD.

Note 6: RL =

∞, digital inputs at GND or VDD.

Note 7: Timing measurement reference level is (VIH + VIL) / 2.

Note 8: If LDAC is activated prior to WR’s rising edge, it must stay low for tLD (or longer) after WR goes high.

ELECTRICAL CHARACTERISTICS (continued)

(VDD = VREF = +2.7V to +5.5V, RL = 10k

Ω, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF

= +3V and TA = +25°C.)

VREF(DC) = 1.5V,

VDD = 3V,

code = FF hex

LDAC Pulse Width (Note 8)

tLD

20

ns

Digital-to-Analog Glitch Impulse

90

nVs

Digital Feedthrough (Note 5)

0.5

nVs

Channel-to-Channel Isolation

(Note 4)

500

nVs

Output Settling Time (Note 3)

6

µs

Signal-to-Noise plus Distortion

Ratio

SINAD

70

dB

60

Multiplying Bandwidth

650

kHz

Wideband Amplifier Noise

60

µVRMS

Output Voltage Slew Rate

0.6

V/µs

Shutdown Recovery Time

tSDR

13

µs

Time to Shutdown

tSDN

20

µs

Power-Supply Voltage

VDD

2.7

5.5

V

Supply Current (Note 6)

IDD

370

700

µA

Shutdown Current

0.001

1

µA

Address to WR Setup

tAS

5

ns

Address to WR Hold

tAH

0

ns

Data to WR Setup

tDS

25

ns

Data to WR Hold

tDH

0

ns

WR Pulse Width

tWR

20

ns

To ±1/2LSB of final value of VOUT

Code 80 hex to code 7F hex

IDD < 5µA

Code 00 to code FF hex

To 1/2LSB, from code 10 to code F0 hex

REF = 0.5Vp-p, VREF(DC) = 1.5V,

VDD = 3V, -3dB bandwidth

From code 00 to code F0 hex

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

REF = 2.5Vp-p at

1kHz

REF = 2.5Vp-p at

10kHz

DYNAMIC PERFORMANCE

POWER SUPPLIES

DIGITAL TIMING (Figure 1) (Note 7)

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