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5P49V5935 Datasheet(PDF) 15 Page - Integrated Device Technology

Part No. 5P49V5935
Description  Generates up to four independent output frequencies
Download  33 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5935 Datasheet(HTML) 15 Page - Integrated Device Technology

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REVISION B 07/13/15
15
PROGRAMMABLE CLOCK GENERATOR
5P49V5935 PRELIMINARY DATASHEET
Cycle-to-Cycle jitter (Peak-to-Peak), multiple output frequencies switching,
differential outputs (1.8V to 3.3V nominal output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
46
ps
Cycle-to-Cycle jitter (Peak-to-Peak), multiple output frequencies switching,
LVCMOS outputs (1.8 to 3.3V nominal output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
74
ps
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs (1.8 to 3.3V
nominal output voltage).
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
0.5
ps
RMS Phase Jitter (12kHz to 20MHz integration range) differential output,
VDDO = 3.465V, 25MHz crystal, 156.25MHz output frequency
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
0.75
1.5
ps
t7
Output Skew
Skew between the same frequencies, with outputs using the same driver
format and phase delay set to 0 ns.
75
ps
t8 3
Startup Time
PLL lock time from power-up, measured after all VDD's have raised above
90% of their target value.
10
ms
t9 4
Startup Time
PLL lock time from shutdown mode
34
ms
Initial frequency accuracy
±2
Frequency stability over temperature
±20
Aging per year
±2
5. Duty Cycle is only guaranteed at max slew rate settings.
4. Actual PLL lock time depends on the loop configuration.
t6
Clock Jitter
t10
Frequency Stability
ppm
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
1. Practical lower frequency is determined by loop filter settings.


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